1. Field of the Invention
The present invention relates to an access priority control system for a main storage for a computer. The system according to the present invention is used for access to a main storage for a computer in which the storage space of the main storage is hierarchically divided. The system according to the present invention can be used for control of an access priority order of a main storage in which a very high probability of existence of successive data of reading or writing, such as vector data, in the same divided storage space is utilized as in the multiple system.
The system according to the present invention is applicable to a vector computer wherein a high speed vector calculation of scientific computation for carrying out a calculation in parallel or in the pipeline manner is used, as well as to a general purpose computer
2. Description of the Related Art
With regard to a main storage unit for a computer in which the storage space is divided into a plurality of segments having different buses and different storage banks, when an access request for read/write is received from a plurality of processors or other external devices, the priority order of the access requests must be determined and a bus conflict between the buses and a busy condition of the storage banks must be controlled.
It is very important to reduce the length of the longest logic path of the control circuit for controlling the priority order and the busy condition checking in a predetermined cycle of the clock signal.
Nevertheless, in the prior art system, the checking of the bus conflict, storage bank busy condition, and prohibition condition are carried out in a single cycle, and the determination of an approval of access to the main storage is carried out in that single cycle. Therefore, the checking of the bus conflict, storage bank busy condition, and prohibition condition must be carried out in a single cycle for all of the access parts, and accordingly, problems arise in that the delay time is very long and the amount of hardware needed is large.
Also, in the prior art system, since the number of access ports is increased and the wirings causes a capacitance effect, the delay time of the longest logic path is increased, and accordingly, an extension of time is required, which has an undesirable effect on the selection of a machine cycle of the system.